1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to one suitable for an application to a 1.5-port SRAM (Static Random Access Memory).
2. Description of Related Art
In conventional semiconductor memory devices, there is a method of configuring an SRAM by, for example, as disclosed in Japanese Unexamined Patent Application Publication No. H10-247691, using four n-channel transistors and two p-channel transistors, two of these n-channel transistors being used as driver transistors, the other two n-channel transistors as transfer gates and the two p-channel transistors as load transistors.
Here, a driver transistor and a load transistor constitute a CMOS inverter, in which the n-channel transistor and the p-channel transistor are connected in series, and a flip-flop is configured by cross-coupling a pair of CMOS inverters.
On the other hand, a 1.5-port SRAM is configured to read-out without depending on a word line signal by adding another p-channel transistor to these four n-channel transistors and two p-channel transistors and using this added p-channel transistor as a read-out transistor.
Here, with such a 1.5-port SRAM, to reduce the surface area of a memory cell, the gate electrode of one of the CMOS inverters including the driver transistor and the load transistor is bent in an L-shape, and used as the gate electrode of a read-out transistor.
However, the following problem arises: When bending the gate electrode of one CMOS inverter including the driver transistor and the load transistor into an L-shape, due to variations in the patterning of the gate electrode, the gate width will vary in a corner part of the gate electrode. Therefore, when the corner part of the gate electrode is located in the vicinity of the read-out transistor, the gate width of the read-out transistor will vary and the performance of the read-out transistor will be reduced.
In consideration of this problem, the present invention is intended to provide a semiconductor memory device that enables a reduction in the variance in gate width of the read-out transistor without increasing the surface area of a memory cell.